A new robust handshake for asymmetric asynchronous micro-pipelines

[[abstract]]In this paper, a new handshake methodology to enhance the performance of the asynchronous micro-pipeline systems is proposed. The proposed handshake methodology has more flexibilities to design an asymmetric asynchronous micro-pipeline system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. Others, the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. An asynchronous micro-pipeline array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35μm CMOS technology, the simulation results show that the proposed new handshake methodology has shortest latency and more robust property as compare with other handshake methodologies.[[conferencetype]]國際[[conferencedate]]20030525~20030528[[booktype]]紙本[[conferencelocation]]Bangkok, Thailan

Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

[[abstract]]Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling[[notice]]補正完畢[[conferencetype]]國際[[conferencedate]]20020107~20020107[[conferencelocation]]Bangalore, Kannad

Design of current mode operational amplifier with differential-input and differential-output

[[abstract]]In this paper, a CMOS implementation of a current operational amplifier (COA) with a differential input and a differential output is described. The amplifier is configured from a differential current mirror input transimpedance stage followed by a differential output transconductance gain stage. A differential mode design technique is proposed and used in the feedback circuit. This configuration is the current mode counterpart of the traditional voltage mode operational amplifier (VOA). In this design, the simulation results exhibit an open-loop differential gain of 51.71 dB with the gain-bandwidth product 314 MHz and a settling time of 14 ns.[[conferencetype]]國際[[conferencedate]]19970609~19970612[[iscallforpapers]]Y[[conferencelocation]]Hong Kon

High efficient 3-input XOR for low-voltage low-power high-speed applications

[[abstract]]A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.[[conferencetype]]國際[[conferencedate]]19990823~19990825[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]Seoul, Kore

The suggestion for CFS CMOS buffer

[[abstract]]Two recent papers, one by Huang et al. (1996) and the other by Cheng et al. (1997), on the driver buffer are commented on. The feedback-controlled split-path CMOS buffer (FS) claims that the 4-split-path buffer can reduce the power and power-delay product. But the voltage of the gates in the output inverter stage is not enough to turn-off the PMOS transistor and the NMOS transistor. Due to this, charge-recovery must be used. The charge-transfer feedback-controlled split-path (CFS) CMOS buffer that has high-speed low-power performance by using transfer of the charge stored in the split output-stage driver to the output node. Thus the power-delay product can be reduced greatly by combining the technology described in the former two papers. The HSPICE simulation results show that the power-delay product of the suggested CMOS buffer is reduced by 20% to 40% in comparison to the conventional CMOS tapered buffer at 100 MHz operation frequency at heavy capacitive load[[conferencetype]]國際[[conferencedate]]19990905~19990908[[booktype]]紙本[[conferencelocation]]Pafos, Cypru

The novel efficient design of XOR/XNOR function for adder applications

[[abstract]]A new concept to implement high performance XOR/XNOR functions that using the pass transistor technique is proposed. It requires only six MOS transistors. Base upon this concept, a new high-speed full adder is proposed for low-power application. We used the modified Karnaugh map (K-map) method to obtain the various pass transistor circuits. We modified the Boolean expression to simplify the control and input signals of the pass transistor logic (PTL) to realize a one-bit full adder. The analysis of the proposed one-bit adders is compared with that of the static CMOS adder, the CPL transmission function adder, the DPL transmission gate adder, and the CPL transmission gate adder. The simulation results shows that the proposed new circuit has the lowest power delay product performance[[conferencetype]]國際[[conferencedate]]19990905~19990908[[booktype]]紙本[[conferencelocation]]Pafos, Cypru

The non-full voltage swing TSPC (NSTSPC) logic design

[[abstract]]In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage[[abstract]]In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage.[[conferencetype]]國際[[conferencedate]]20000828~20000830[[booktype]]紙本[[conferencelocation]]Cheju, Kore

Role of SiNx Barrier Layer on the Performances of Polyimide Ga2O3-doped ZnO p-i-n Hydrogenated Amorphous Silicon Thin Film Solar Cells

In this study, silicon nitride (SiNx) thin films were deposited on polyimide (PI) substrates as barrier layers by a plasma enhanced chemical vapor deposition (PECVD) system. The gallium-doped zinc oxide (GZO) thin films were deposited on PI and SiNx/PI substrates at room temperature (RT), 100 and 200 °C by radio frequency (RF) magnetron sputtering. The thicknesses of the GZO and SiNx thin films were controlled at around 160 ± 12 nm and 150 ± 10 nm, respectively. The optimal deposition parameters for the SiNx thin films were a working pressure of 800 × 10−3 Torr, a deposition power of 20 W, a deposition temperature of 200 °C, and gas flowing rates of SiH4 = 20 sccm and NH3 = 210 sccm, respectively. For the GZO/PI and GZO-SiNx/PI structures we had found that the GZO thin films deposited at 100 and 200 °C had higher crystallinity, higher electron mobility, larger carrier concentration, smaller resistivity, and higher optical transmittance ratio. For that, the GZO thin films deposited at 100 and 200 °C on PI and SiNx/PI substrates with thickness of ~1000 nm were used to fabricate p-i-n hydrogenated amorphous silicon (α-Si) thin film solar cells. 0.5% HCl solution was used to etch the surfaces of the GZO/PI and GZO-SiNx/PI substrates. Finally, PECVD system was used to deposit α-Si thin film onto the etched surfaces of the GZO/PI and GZO-SiNx/PI substrates to fabricate α-Si thin film solar cells, and the solar cells’ properties were also investigated. We had found that substrates to get the optimally solar cells’ efficiency were 200 °C-deposited GZO-SiNx/PI

Retraction and Generalized Extension of Computing with Words

Fuzzy automata, whose input alphabet is a set of numbers or symbols, are a formal model of computing with values. Motivated by Zadeh's paradigm of computing with words rather than numbers, Ying proposed a kind of fuzzy automata, whose input alphabet consists of all fuzzy subsets of a set of symbols, as a formal model of computing with all words. In this paper, we introduce a somewhat general formal model of computing with (some special) words. The new features of the model are that the input alphabet only comprises some (not necessarily all) fuzzy subsets of a set of symbols and the fuzzy transition function can be specified arbitrarily. By employing the methodology of fuzzy control, we establish a retraction principle from computing with words to computing with values for handling crisp inputs and a generalized extension principle from computing with words to computing with all words for handling fuzzy inputs. These principles show that computing with values and computing with all words can be respectively implemented by computing with words. Some algebraic properties of retractions and generalized extensions are addressed as well.Comment: 13 double column pages; 3 figures; to be published in the IEEE Transactions on Fuzzy System

Modulating Microglia/Macrophage Activation by CDNF Promotes Transplantation of Fetal Ventral Mesencephalic Graft Survival and Function in a Hemiparkinsonian Rat Model

Parkinson's disease (PD) is characterized by the loss of dopaminergic neurons in substantia nigra pars compacta, which leads to the motor control deficits. Recently, cell transplantation is a cutting-edge technique for the therapy of PD. Nevertheless, one key bottleneck to realizing such potential is allogenic immune reaction of tissue grafts by recipients. Cerebral dopamine neurotrophic factor (CDNF) was shown to possess immune-modulatory properties that benefit neurodegenerative diseases. We hypothesized that co-administration of CDNF with fetal ventral mesencephalic (VM) tissue can improve the success of VM replacement therapies by attenuating immune responses. Hemiparkinsonian rats were generated by injecting 6-hydroxydopamine (6-OHDA) into the right medial forebrain bundle of Sprague Dawley (SD) rats. The rats were then intrastriatally transplanted with VM tissue from rats, with/without CDNF administration. Recovery of dopaminergic function and survival of the grafts were evaluated using the apomorphine-induced rotation test and smallanimal positron emission tomography (PET) coupled with [F-18] DOPA or [F-18] FE-PE2I, respectively. In addition, transplantation-related inflammatory response was determined by uptake of [F-18] FEPPA in the grafted side of striatum. Immunohistochemistry (IHC) examination was used to determine the survival of the grated dopaminergic neurons in the striatum and to investigate immune-modulatory effects of CDNF. The modulation of inflammatory responses caused by CDNF might involve enhancing M2 subset polarization and increasing fractal dimensions of 6-OHDA-treated BV2 microglial cell line. Analysis of CDNF-induced changes to gene expressions of 6-OHDA-stimulated BV2 cells implies that these alternations of the biomarkers and microglial morphology are implicated in the upregulation of protein kinase B signaling as well as regulation of catalytic, transferase, and protein serine/threonine kinase activity. The effects of CDNF on 6-OHDA-induced alternation of the canonical pathway in BV2 microglial cells is highly associated with PI3K-mediated phagosome formation. Our results are the first to show that CDNF administration enhances the survival of the grafted dopaminergic neurons and improves functional recovery in PD animal model. Modulation of the polarization, morphological characteristics, and transcriptional profiles of 6-OHDA-stimualted microglia by CDNF may possess these properties in transplantation-based regenerative therapies.Peer reviewe